This invention is in the field of wireless communications, and is more specifically directed to the digital coding and modulation of broadband signals in such communications.
The popularity of mobile wireless communications has increased dramatically over recent years. It is expected that this technology will become even more popular in the foreseeable future, both in modem urban settings and also in rural or developing regions that are not well served by line-based telephone systems. This increasing wireless traffic strains the available communications bandwidth for a given level of system infrastructure. As a result, there is substantial interest in increasing bandwidth utilization of wireless communications system to handle this growth in traffic.
This trend toward heavier usage of wireless technologies for communications, in combination with the advent of so-called third-generation, or “3G”, wireless communications to carry not only voice, but also data, video, and other high data rate payloads, will require continuing improvements in the processing capabilities of the communications equipment. In particular, the higher required data rates will require corresponding increases in the digital processing of the communications payloads.
Modern digital communications technology utilizes multiple-access techniques to increase bandwidth utilization, and thus to carry more wireless traffic. Under current approaches, both time division multiple access (TDMA) and code division multiple access (CDMA) techniques are used in the art to enable the simultaneous operation of multiple communication sessions, or wireless “connections”, each involving voice communications, data communications, or any type of digital payload. As evident from the name, TDMA communications are performed by the assignment of time slots to each of multiple communications, with each conversation transmitted alternately over short time periods. CDMA technology, on the other hand, permits multiple communication sessions to be transmitted simultaneously in both time and frequency, by modulating the signal with a specified code. On receipt, application of the code will recover the corresponding conversation, to the exclusion of the other simultaneously received conversations.
In both TDMA and CDMA communications, according to conventional and expected next-generation approaches, digital coding is applied for various purposes. An example of a typical digital code is convolutional coding, which inserts redundancy into the digital word stream being transmitted. In broadband communications, successive digital words in the transmitted digital datastream are effectively split into multiple subchannels, each subchannel being separately spread and encoded. Convolutional coding is applied to each subchannel, with the inserted redundancy providing the ability of forward error correction at the receiver. This convolutional coding thus effectively increases the signal-to-noise ratio of the wireless transmission.
FIG. 1 illustrates convolutional coder 5, constructed according to conventional techniques, and which in this example is based on the 3GPP 25.212 third-generation standard. In convolutional coder 5 of FIG. 1, the code rate is 1/3, considering that the input bitstream x(k) applies single bits, and that three output bitstreams y0(k), y1(k), y2(k) are generated. The constraint length of this example is nine, considering the eight delay stages 27 through 20. The current state of input x(k) and the eight previous states of input x(k) are used to produce the output bitstreams y0(k), y1(k), y2(k). As shown in FIG. 1, convolutional coder 5 also includes exclusive-OR functions 4, arranged to implement the desired convolutional code. Each exclusive-OR function 4 has an input from one of delay stages 2, and an input from a previous exclusive-OR function 4 (or directly from input x(k)).
The positions of the exclusive-OR functions 4 determine the code generator polynomials G0, G1, G2 that generate the outputs y0(k), y1(k), y2(k), respectively. According to the conventional nomenclature, the convolutional code of FIG. 1 is referred to as K=9, (5578, 6638, 7118), with generator polynomials G0=5578, G1=6638, and G2=7118. Outputs y0(k), y1(k), y2(k) are presented once per cycle, and thus produce a three bit sequence that is representative of a corresponding input bit x(k), and that includes redundant information from which forward error correction techniques can recover the true signal from a corrupted received transmission.
As shown in FIG. 1, convolutional coder 5 can be implemented by way of a shift register containing delay stages 2, and combinatorial logic for realizing exclusive-OR functions 4. However, in such an implementation, either the convolutional code must be hard-wired into convolutional coder 5, or alternatively the placement of a selectable exclusive-OR function 4 for each delay stage output and each generator polynomial (e.g., twenty-four functions 4 in convolutional coder 5 of FIG. 1), must be implemented. Such an architecture may turn out to be costly, yet with limited performance.
Another type of coding performed in conventional digital wireless communications is the application of a scrambling code. As currently used, this scrambling code is a cell-specific sequence that is applied to the encoded data stream in a wireless communication. The receiving element, with knowledge of the cell-specific code, can thus distinguish communications in its cell from those that are received from wireless units in physically neighboring cells.
By way of further background, FIG. 2 illustrates a conventional scrambling code generator 10. As mentioned above and as known in the art, the application of a scrambling code enables a wireless receiver to resolve those communications received from its own physical cell from those communications received from other cells, and unintended for receipt by that wireless element. As known in the art, scrambling code generator 10 generates in-phase and quadrature components Ic(k), Qc(k), respectively, of a cell-specific scrambling code. These components are applied to respective in-phase and quadrature components of a datastream, modulated according to a quadrature amplitude modulation (QAM) constellation.
Scrambling code generator 10 of FIG. 2 includes delay stage sequence 15I and delay stage sequence 15Q, each sequence having eighteen delay stages numbered from 0 to 17 in this example. A sample of in-phase code component Ic(k) is generated by exclusive-OR function 19I, which receives the outputs of the final delay stages, numbered 0, in delay stage sequences 15I, 15Q. A corresponding sample of quadrature code component Qc(k) is generated by exclusive-OR function 19Q, which receives the outputs of feed-forward exclusive-OR functions 12, 16, each of which receive the contents of delay stages 15I, 15Q in the corresponding sequences, selected according to the particular scrambling code polynomial. In this example, feed-forward exclusive-OR function 12 receives the outputs of the delay stages numbered 4, 6, and 15 in delay stage sequence 15I4; feed-forward exclusive OR function 16 receives the outputs of the delay stages numbered 5 and 15 in delay stage sequence 15Q. The contents of delay stages 15I, 15Q are regenerated by feedback exclusive-OR functions 14, 18. In this example, feedback exclusive-OR function 14 receives inputs from the final delay stage (numbered 0) and the delay stage numbered 7 in delay stage sequence 15I, and forwards its output to the input of the first delay stage, numbered 17, in delay stage sequence 15I. Also in this example, feedback exclusive-OR function18 receives inputs from the final delay stage 15Q and from the delay stages numbered 5 and 7 in delay stage sequence 15Q, and has its output connected to the input of the first delay stage, numbered 17, in delay stage sequence 15Q.
Similarly as in the case of convolutional coder 5, scrambling code generator 10 may be realized by way of shift registers and combinatorial logic. However, in order to provide variations in the scrambling code to be applied, the exclusive-OR functions 12 through 18 must be selectable according to the code generating polynomial. Such flexibility requires a large number of potential connections both in and out of exclusive-OR functions, as well as circuitry for selectably enabling and disabling these potential connections.
By way of further background, conventional integer multiplier circuits, such as used in microprocessors and digital signal processors, are arranged to perform successive addition. For example, a typical conventional integer multiplier adds selected left-shifted replications of the multiplicand, with the summed shifted multiplicands being those corresponding to “1” bits in the multiplier; “0” bits of the multiplier block the addition of corresponding shift positions of the multiplicand from being included in the product. The additions include the use of carry-in and carry-out signals.
FIG. 3 illustrates conventional parallel multiplier 20, for multiplying two four-bit digital values X, Y. This construction is disclosed in U.S. Pat. No. 4,598,382. Multiplier 20 includes an array of sixteen full two-bit adder units U1 through U16. Adder units U are arranged in four rows of four, each row associated with one bit of multiplier Y. For example, adder units U1 through U4 are associated with multiplier bit Y1, adder units U5 through U8 are associated with multiplier bit Y2, and so on. Each row of adder units U receive the four bits X1 through X4 of the multiplicand, and the associated bit of multiplier Y for that row. In operation, multiplicand X is added to itself, left-shifted (i.e., multiplied by two), depending upon the state of the ascending bits of multiplier Y, with carries propagating accordingly. The resulting product word P is thus the binary integer product of multiplicand X and multiplier Y.
The construction of each adder unit U in multiplier 20 is illustrated with respect to adder unit U16. As shown in FIG. 3, adder unit U16 includes full two-bit adder 22, and AND gate 24. AND gate 24 receives a bit of multiplicand X (bit X4 in this example, for adder unit U16) and a bit of multiplier Y (bit Y4 in this example, for adder unit U16), and outputs addend A corresponding to the logical AND of these multiplier and multiplicand bits. In this way, the state of multiplier bit Y determines whether the corresponding multiplicand bit X is included in the sum performed by full adder 22. Addend B, presented to full adder 22, depends upon the particular position of adder unit U within multiplier 20. Adder units U1 through U4, in the top row of multiplier 20, simply receive a “0” bit for their addends B. Later rows of adder units U in multiplier 20 receive the results of earlier rows. For example, adder units U5 through U7, left-shifted by one position in the second row, receive sum bits S from a corresponding adder U2 through U4 in the first row; specifically, adder unit U5 receives the sum output S of adder unit U2, adder unit U6 receives the sum output S of adder unit U3, and adder unit U7 receives the sum output S of adder unit U4. The most significant adder unit U in each of the later rows receives, as its addend B, the carry output C of the most significant adder unit U in the previous row; for example, adder unit U8 receives the carry out bit C from adder unit U4. Each adder unit U other than the least significant position receives carry in bit C′, corresponding to the carry out C bit of its least significant neighbor, and applies this carry in C′ to its full adder 22.
The sum output bits of the least significant adder units U1, U5, U9 in earlier rows are presented as product bits P1, P2, P3, respectively. The sum output bits S from adder units U in the last row are presented as the higher order product bits. In the example of multiplier 20 in FIG. 3, the sum output bits S from adder units U13 through U16 correspond to product bits P4 through P7, respectively. The carry out bit C from the most significant adder unit U in the last row, adder unit U16 in this example, becomes the most significant product bit, P8 in this example.